Shaoshan Liu is a Ph.D. candidate. His research interests include high performance computer architecture, reconfigurable systems, runtime systems, and biomedical engineering. Shaoshan’s Ph.D. thesis title is Synchronization and Value Prediction Mechanisms in Many-Core Architectures, in which he studies the effects of fine-grained synchronization and value prediction techniques in enhancing the performance of many-core architectures. During his Ph.D. study, Shaoshan also worked and researched in institutions including Broadcom (as a device verification and test engineer), Intel Research (as a research intern to develop garbage collection algorithms for parallel systems), at INRIA, a major French research center (as a computer system researcher focusing on HPC applications), as well as at Microsoft Research (as a research intern focusing on embedded systems). Shaoshan holds a BS and a MS in Computer Engineering, also a MS in Biomedical Engineering, all from UC Irvine. Some of his research has already been published in major venues, including one Best Paper Award at ACSAC 2008 and one article in IEEE Transactions on Computers.