Parallel On-Chip Simultaneous Multithreading


Description of the Project

The shrinking dimensions of future VLSI processes present challenges to creating future processors. Processors are capable of more logic, which increases critical paths. Higher parasitic resistance and capacitance increase the routing delays. Two approaches to solving these problems are On-Chip Multiprocessing (CMP) and Simultaneous Multithreading (SMT). CMP increases layout efficiency, which allows more functional units and a faster clock rate. However, CMP suffers from hardware partitioning of functional resources. SMT increases functional unit utilization by simultaneously issuing instructions from multiple threads. However, a wide-issue SMT suffers from layout and technology implementation problems. This research combines these two techniques and trades off CMP for SMT threads. The analysis shows that the combination provides higher throughput performance than either individual technique. This research uses silicon resources as the basis for comparison and finds a nearly three-fold increase in CMP throughput. It also shows the area overhead of SMT on each processor and how it scales by O(d2tlog2(t)) due to the remapping tables, and O(d3t) from the register files. The area overhead is quantified, and ISA and microarchitecture techniques are discussed to best take advantage of SMT while minimizing the layout impact.


Selected publications

Parallel On-Chip Simultaneous Multithreading- PhD Thesis

Area and System Clock Effects on SMT/CMP Processors(Postscript) , (MS Word) ,
James Burns and Jean-Luc Gaudiot
Parallel Architectures and Compilation Techniques (PACT 2001), Barcelona, Spain, September 2001


SMT Fetch Bottleneck with Multiple Block Fetch

James Burns and Jean-Luc Gaudiot
Workshop on MULTI-THREADED EXECUTION, ARCHITECTURE and COMPILATION (MTEAC-4) held in conjunction with the 33rd International Symposium on Microarchitecture (MICRO-33) December 10, 2000 in Monterey, California.


Quantifying the SMT Layout Overhead - Does SMT Pull Its Weight?

Jim Burns and Jean-Luc Gaudiot
Proceedings of the 6th High Performance Computer Architecture Conference (HPCA-6) January 2000


Exploring the SMT Fetch Bottleneck

James Burns and Jean-Luc Gaudiot
Proceedings of the Workshop on Multithreaded Execution, Architecture and Compilation(MTEAC'99), 1999, Orlando, Florida


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