Jean-Luc Gaudiot

Professor & Chair, Department of Electrical Engineering and Computer Science, University of California - Irvine

Fellow, IEEE, 1999

Fellow, AAAS, 2007

Professor Jean-Luc Gaudiot received the Diplôme d'Ingénieur from the École Supérieure d'Ingénieurs en Electronique et Electrotechnique, Paris, France in 1976 and the M.S. and Ph.D. degrees in Computer Science from the University of California, Los Angeles in 1977 and 1982, respectively.

He is currently a Professor in the Electrical Engineering and Computer Science Department at the University of California, Irvine. Prior to joining UCI in January 2002, he was a Professor of Electrical Engineering at the University of Southern California since 1982, where he served as Director of the Computer Engineering Division for three years. He has also designed distributed microprocessor systems at Teledyne Controls, Santa Monica, California (1979-1980) and performed research in innovative architectures at the TRW Technology Research Center, El Segundo, California (1980-1982). He frequently acts as consultant to companies that design high-performance computer architectures, and has served as an expert witness in patent infringement and product liability cases. His research interests include multithreaded architectures, fault-tolerant multiprocessors, and implementation of reconfigurable architectures. He has published over 150 journal and conference papers. His research has been sponsored by NSF, DoE, and DARPA, as well as a number of industrial organizations.

In January 2006, he became the first Editor-in-Chief of the IEEE Computer Architecture Letters, a new publication of the IEEE Computer Society, which he helped found to the end of facilitating short, fast turnaround of fundamental ideas in the Computer Architecture domain. From 1999 to 2002, he was the Editor-in-Chief of the IEEE Transactions on Computers. In June 2001, he was elected chair of the IEEE Technical Committee on Computer Architecture, and re-elected in June 2003 for a second two-year term.

Dr. Gaudiot is a member of AAAS, ACM, and IEEE. He has also chaired the IFIP Working Group 10.3 (Concurrent Systems). He was co-General Chairman of the 1992 International Symposium on Computer Architecture, Program Committee Chairman of the 1993 IFIP Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, the 1993 IEEE Symposium on Parallel and Distributed Processing (Systems Track), the 1995 Parallel Architectures and Compilation Techniques Conference (PACT ‘95), the High Performance Computer Architecture conference in 1999 (HPCA-5), and the 2005 International Parallel and Distributed Processing Symposium.

In 1999, he became a Fellow of the IEEE, “For Contributions to the Programmability and Reliability of Dataflow Architectures.” He was elevated to the rank of AAAS Fellow in 2007, “For Distinguished Contributions to the Design and Analysis of Highly Efficient Multiprocessor and Memory System Architectures.”

Dr. Gaudiot is an avid pilot and he brings to his leisure time his love for teaching by being a flight instructor (both primary and instrument).

Jean-Luc Gaudiot's Résumé

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