HiDISC
- Hierarchical
Decoupled
Instruction
Stream
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HiDISC is a hierarchical decoupled instruction stream architecture. Three individual processors for computing, memory access and cache management are developed for a novel high performance decoupled architecture. Computing instructions, memory access instructions and cache management instructions are partitioned and fetched into each of the processors. HiDISC is designed to resolve the memory wall problem by instruction-level parallelism. Therefore, this new architecture can provide significant improvement especially in data intensive program such as image recognition and data management.
* This project is funded by DARPA/ITO
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