HiDISC - Hierarchical Decoupled Instruction Stream Computer


HiDISC is a hierarchical decoupled instruction stream architecture. Three individual processors for computing, memory access and cache management are developed for a novel high performance decoupled architecture. Computing instructions, memory access instructions and cache management instructions are partitioned and fetched into each of the processors.


HiDISC is designed to resolve the memory wall problem by instruction-level parallelism. Therefore, this new architecture can provide significant improvement especially in data intensive program such as image recognition and data management.


- Final poster


* This project is funded by DARPA/ITO



DARPA Data Intensive Systems PI meeting:




  DARPA Presentation:
  Final Report:


  • HiDISC: A Decoupled Architecture for Data-Intensive Applications
    Won W. Ro, Jean-Luc Gaudiot, Stephen P. Crago, and Alvin M. Despain
    The 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), Nice, France, April 22-26, 2003

  • Compiler Support for Dynamic Speculative Pre-Execution
    Won W. Ro and Jean-Luc Gaudiot
    The 7th Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT-7) in conjunction with HPCA-9, Anaheim, California, February 8, 2003

  • Memory Latency: to Tolerate or to Reduce?
    Amol Bakshi, Jean-Luc Gaudiot, Wen-Yen Lin, Manil Makhija, Viktor K. Prasanna, Wonwoo Ro, and Chulho Shin
    Invited paper at the 12th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'00), Sao Pedro, Brazil, October 24-27, 2000

  • A High-Performance, Hierarchical Decoupled Architecture
    Stephen P. Crago, Alvin Despain, Jean-Luc Gaudiot, Manil Makhija,Wonwoo Ro, and Apoorv Srivastava
    Proceedings of the Memory access Decoupling for superscalar and multiple issue Architectures (MEDEA) Workshop in conjunction with PACT2000, Philadelphia, October 15, 2000


  Return to the PASCAL project page